SA9604A

sames

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5.6 Synchronised Reading of Registers

The SA9604A integrated circuit updates the registers on a continual basis. The

SA9604A register content in latched onto the SPI interface as soon as a read

command has been detected or the next register is addressed during continual

access. The registers can be accessed at any time however for maximum stability

the time between readings must be in multiples of 8 mains cycles. The internal offset

cancellation procedure requires 8 mains cycles to complete. The registers are not

reset after access, so in order to determine the correct register value the previous

value read must be subtracted from the current reading. This methodology holds

true for Active, Reactive and Voltage registers. The data read from the registers

SPI TIMING

Parameter

t1

t2

t3

t4

Description

SCK rising edge for data valid

Setup time for DI and CS before the rising edge

of SCK

SCK min high time

SCK min low time

Unit

µS

µS

µS

µS

Max

1,160

Min

0,560

0,625

0,625