SC653 datasheet(15/22 Pages) SEMTECH

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SC653

PCB Layout Considerations

The layout diagram in Figure 2 illustrates a proper

two-layer PCB layout for the SC653 and supporting com-

ponents. Following fundamental layout rules is critical for

achieving the performance specified in the Electrical

Characteristics table. The following guidelines

are recommended when developing a PCB layout:

Place all bucket, bypass, and decoupling capaci-

tors — C1, C2, CIN, COUT, CLDO1, CLDO2, and

CBYP as close to the device as possible.

All charge pump current passes through IN,

OUT, and the bucket capacitor connection pins.

Ensure that all connections to these pins make

use of wide traces so that the resistive drop on

each connection is minimized.

The thermal pad should be connected to the

ground plane using multiple vias to ensure

proper thermal connection for optimal heat

transfer.

•

Applications Information (continued)

The following capacitors — CLDO1, CLDO2, and

CBYP should be grounded together through an

isolated copper island. Using no vias, connect

the island only, to pin 7 as shown in Figure 2.

Figure 3 shows only the vias that should be con-

nected to the ground plane with multiple vias.

Make all ground connections to a solid ground

plane as shown in Figure 4.

All LDO output traces should be made as wide

as possible to minimize resistive losses.

•

TBD Figure 4 — Layer 2

TBD Figure 2 — Recommended PCB Layout

TBD Figure 3 — Layer 1

OUT

SC653

GND2

COUT

Island for

pin 7 GND1

(no vias)

Ground Layer

CBYP

Keep gap

open

Vias to

ground

plane

CLDO2

CLDO1

CIN

Figure 2 — Recommended PCB Layout

Figure 3 — Layer 1

Figure 4 — Layer 2

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