SC2595STRT datasheet(6/12 Pages) SEMTECH

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SC2595

PRELIMINARY

POWER MANAGEMENT

Overview

Double Data Rate (DDR) SDRAM was defined by JEDEC

1997. Its clock speed is the same as previous SDRAM

but data transfers speed is twice than previous SDRAM.

By now, the requirement voltage range is changed from

3.3V to 2.5V; the power dissipation is smaller than

SDRAM. For above reasons, it is very popular and widely

used in M/B, N/B, Video-cards, CD ROM drives, Disk

drives.

Regarding the DDR power management solution, there

are two topologies can be selected for system design-

ers. One is switching mode regulator that has bigger sink/

source current capability, but the cost is higher and the

board space needed is bigger. Another solution is linear

mode regulator, which costs less, and needs the less

board space. For two DIMM motherboards, system de-

signers usually choose the linear mode for DDR power

management solution.

Applications

TTTTTypical Application Cir

ypical Application Cir

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eforms

orms

Two different application circuits are shown below in Fig-

ure 1 to Figure 2. Each circuit is designed for specific

condition. More details are described below. See Note

1. Below for recommended power up sequencing.

Application_1: Standar

Application_1: Standard SS

d SS

d SSTL

TL-2 Application

-2 Application

The AV

CC pins, the PVCC pin, and the VDDQ pin can be tied

together for SSTL-2 application. It only needs a 2.5V

power rail for normal operation. System designer can

save the PCB space and reduce the cost. Please refer

to figures 3 to 4 for test waveforms.

Figure 1: Standard SSTL-2 application

Application Information

Application_2: Lower Power Loss Configuration

fffffor SS

or SS

or SSTL

TL-2

-2

If power loss is a major concern, separated the PV

CC form

the AV

CC and the VDDQ will be a good choice. The PVCC can

operate at lower voltage (1.8V to 2.5V). If 2.5V voltage

is applied on AV

CC and the VDDQ, but the source current is

lower due to the lower operating voltage applied on the

CC.

Please find the relative test result in Figures 5, 11

and 12.

Figure 2: Lower power loss for SSTL-2 application

Notes:

(1) Power up of AV

CC, PVCC and VDDQ supplies.

(a) The preferred mode of operation is when the

CC, PVCC and VDDQ pins are tied together to a

single supply.

(b) If and when AV

CC, PVCC pins are tied to a supply

separate to that of the V

DDQ supply pin; then

the V

DDQ supply should lead AVCC, PVCC supply or

the V

DDQ supply and the AVCC, PVCC supply should

rise simultaneously.

CC, PVCC and VDDQ supply pins are con

nected in a way such that, AV

CC, PVCC supplies

precedes V

DDQ supply; then VTT output precedes

DDQ. This can cause the SDRAM device to latch-

up, which may cause permanent damage to the

SDRAM.

Cin2

1uF

Cout1

220uF

VDD

Cin1

68uF

Cout2

10uF

SC2595

GND

VSENSE

VREF

VDDQ

AVCC

PVCC

VTT

Cref

10nF

Csence

2.2uF

2.5V

1.25V

5.1

10uF

Cin2

1.25V

Csense

2.2uF

1uF

Cin2

Vin

2.5V

Cref

10nF

VTT

Cout1

220uF

SC2595

GND

VSENSE

VREF

VDDQ

AVCC

PVCC

VTT

Cddq

1uF

VDD

1.8V to 2.5V

Cin1

68uF

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