ADP2302ARDZ-R7 datasheet(15/28 Pages) AD

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ADP2302/ADP2303

Rev. 0 | Page 15 of 28

Table 5. Correlation Between fSW and VFB

FB Pin Voltage

Switching Frequency

VFB ≥ 0.6 V

fSW

0.4 V < VFB < 0.6 V

1/2 fSW

0.2 V < VFB ≤ 0.4 V

1/4 fSW

VFB ≤ 0.2 V

1/8 fSW

When a hard short (VFB ≤ 0.2 V) is removed, a soft start cycle

is initiated to regulate the output back to its level during normal

operation, which helps to limit the inrush current and prevent

possible overshoot on the output voltage.

UNDERVOLTAGE LOCKOUT (UVLO)

The ADP2302/ADP2303 have fixed, internally set undervoltage

lockout circuitry (UVLO). If the input voltage drops below

2.4 V, the ADP2302/ADP2303 shut down and the MOSFET

switch turns off. After the voltage rises above 2.7 V, the soft

start period is initiated, and the part is enabled.

THERMAL SHUTDOWN (TSD)

If the ADP2302/ADP2303 junction temperature rises above 150°C,

the thermal shutdown circuit disables the chip. Extreme junction

temperature can be the result of high current operation, poor

circuit board design, or high ambient temperature. A 15°C

hysteresis is included so that when thermal shutdown occurs,

the ADP2302/ADP2303 do not return to operation until the on-

chip temperature drops below 135°C. When the devices recover

from thermal shutdown, a soft start is initiated.

OVERVOLTAGE PROTECTION (OVP)

The ADP2302/ADP2303 provide an overvoltage protection

feature to protect the system against an output short to a higher

voltage supply. If the feedback voltage is above 0.880 V, the

internal high-side MOSFET is turned off, until the voltage at FB

decreases to 0.850 V. At that time, the ADP2302/ADP2303

resume normal operation.

POWER GOOD

The PGOOD pin is an active high, open-drain output and

requires a resistor to pull it up to a voltage (<20.0 V). A high

indicates that the voltage on the FB pin (and therefore the

output voltage) is above 87.5% of the reference voltage. A low

indicates that the voltage on the FB pin is below 85% of the

reference voltage. There is a 32-cycle waiting period after FB is

detected as being in or out of bounds.

CONTROL LOOP

The ADP2302/ADP2303 are internally compensated to minimize

external component count and cost. In addition, the built-in

slope compensation helps to prevent subharmonic oscillations

when the ADP2302/ADP2303 operate at a duty cycle greater

than or close to 50%.

ADP2302ARDZ-R7 数据表(PDF) 15 Page - Analog Devices

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