ADP160/ADP161

Rev. 0 | Page 12 of 20

THEORY OF OPERATION

The ADP160/ADP161 are ultralow quiescent current, low dropout

linear regulators that operate from 2.2 V to 5.5 V and can provide

up to 150 mA of output current. Drawing only 560 nA (typical)

at no load and a low 42 μA of quiescent current (typical) at full

load makes the ADP160 ideal for battery-operated portable

equipment. Shutdown current consumption is typically 50 nA.

Using new innovative design techniques, the ADP160 provides

ultralow quiescent current and superior transient performance

for digital and RF applications. The ADP160 is also optimized

for use with small 1 μF ceramic capacitors.

REFERENCE

SHORT CIRCUIT,

UVLO, AND

THERMAL

PROTECT

SHUTDOWN

R1

R2

VOUT

VIN

GND

EN

R3

ADP160

Figure 28. Internal Block Diagram, Fixed Output with Output Discharge Function

REFERENCE

SHORT CIRCUIT,

UVLO, AND

THERMAL

PROTECT

SHUTDOWN

VOUT

ADJ

VIN

GND

EN

R1

ADP161

Figure 29. Internal Block Diagram, Adjustable Output with

Output Discharge Function

Internally, the ADP160 consists of a reference, an error amplifier,

a feedback voltage divider, and a PMOS pass transistor. Output

current is delivered via the PMOS pass device, which is controlled

by the error amplifier. The error amplifier compares the reference

voltage with the feedback voltage from the output and amplifies

the difference. If the feedback voltage is lower than the reference

voltage, the gate of the PMOS device is pulled lower, allowing

more current to pass and increasing the output voltage. If the

feedback voltage is higher than the reference voltage, the gate

of the PMOS device is pulled higher, allowing less current to pass

and decreasing the output voltage.

The adjustable ADP161 has an output voltage range of 1.0 V to

4.2 V. The output voltage is set by the ratio of two external resistors,

as shown in Figure 2. The device servos the output to maintain

the voltage at the ADJ pin at 1.0 V referenced to ground. The

current in R1 is then equal to 1.0 V/R2, and the current in R1 is

the current in R2 plus the ADJ pin bias current. The ADJ pin

bias current, 10 nA at 25°C, flows through R1 into the ADJ pin.

The output voltage can be calculated using the equation:

The value of R1 should be less than 200 kΩ to minimize errors in

the output voltage caused by the ADJ pin bias current. For example,

when R1 and R2 each equal 200 kΩ, the output voltage is 2.0 V.

The output voltage error introduced by the ADJ pin bias current is

2 mV or 0.10%, assuming a typical ADJ pin bias current of

10 nA at 25°C.

Note that in shutdown, the output is turned off and the divider

current is zero.

The ADP160/ADP161 also include an output discharge resistor to

force the output voltage to zero when the LDO is disabled. This

ensures that the output of the LDO is always in a well-defined state,

whether it is enabled or not.

The ADP160 is available in 15 output voltage options, ranging from

1.2 V to 4.2 V. The ADP160/ADP161 use the EN pin to enable

and disable the VOUT pin under normal operating conditions.

When EN is high, VOUT turns on, and when EN is low, VOUT

turns off. For automatic startup, EN can be tied to VIN.