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FS8108 数据表(PDF) 7 Page - Princeton Technology Corp |
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FS8108 数据表(HTML) 7 Page - Princeton Technology Corp |
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7 / 10 page ![]() FS8108 Page 7 Jan 2003 ignored, the next 13 data bits are loaded to the 13-bit R-counter latch and the remaining 3 LSBs are used to control testing modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 = low. To disable LD output (i.e. set LD low), R14 should be set low. Serial input data timing waveforms are shown in Fig. 2. Fig. 1 – Serial input data format Fig. 2 – Serial input data timing waveforms 18-bit data for N-counter 13-bit data for R-counter ignored t SU1 t SU2 t HOLD DATA CLK LE DATA CLK LE 23 4567 89 10 11 12 13 14 15 16 17 1 18 19 |
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