FS8170

Page 11

July 2005

Multi-function Lock Detect Output (FOLD)

A digital lock detect function is included with the phase detector through an internal digi-

tal filter to produce a logic level output which is available on the FOLD output pin. The

criterion of lock indication depends on the period of the crystal oscillator reference. The

lock dectect output is HIGH whenever the phase error between phase detector inputs is

less than 2 times of the crystal period for more than three consecutive comparison cycles,

otherwise is low. Note that LD becomes HIGH during the power saving mode. The LD

output is depicted in Fig. 3 as well.

Power-down Control (EN)

By setting the pin EN to LOW, the chip enters into power-down mode, reducing the cur-

rent consumption. During the power-down mode, the phase detector output, DO, is set to

its high impedance. Normal operation mode resumes when EN is switched to HIGH. To

prove a smooth start-up condition, an intermittent control circuit is activated when the

device returns to normal operation. Due to the unknown relationship between f

after returning from power-down, the PFD output is unpredictable and may give rise to a

significant jump in the VCO’s frequency which will result in an increased lock-up time.

To prevent this, the FS8170 employs an intermittent control circuit to limit the magnitude

of the error signal generated by the phase detector when it returns to normal operation,

thus ensuring a much quicker return to the fully phase-locked condition.

Table 8: Setting for the pin EN

EN

Status

H

Normal operation mode

L

Power-down mode