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35C 数据表(PDF) 13 Page - Renesas Technology Corp |
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35C 数据表(HTML) 13 Page - Renesas Technology Corp |
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13 / 57 page  R8C/35C Group 2. Central Processing Unit (CPU) R01DS0006EJ0100 Rev 1.00 Page 13 of 54 Aug. 24, 2010 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. |
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