AD7441/AD7451

Rev. D | Page 16 of 24

SERIAL INTERFACE

Figure 2 and Figure 3 show detailed timing diagrams for the

serial interface of the AD7451 and the AD7441, respectively.

The serial clock provides the conversion clock and also controls

the transfer of data from the device during conversion.

CS initiates the conversion process and frames the data transfer.

The falling edge of CS puts the track-and-hold into hold mode

and takes the bus out of three-state. The analog input is sampled

and the conversion initiated at this point. The conversion requires

16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold

goes back into track mode on the next SCLK rising edge, as

shown at Point B in Figure 2 and Figure 3. On the 16th SCLK

falling edge, the SDATA line goes back into three-state.

If the rising edge of CS occurs before 16 SCLKs have elapsed,

the conversion is terminated and the SDATA line goes back into

three-state.

The conversion result from the AD7441/AD7451 is provided on

the SDATA output as a serial data stream. The bits are clocked

out on the falling edge of the SCLK input. The data stream of

the AD7451 consists of four leading zeros followed by 12 bits

of conversion data, provided MSB first. The data stream of the

AD7441 consists of four leading zeros, followed by the 10 bits

of conversion data, followed by two trailing zeros, which is also

provided MSB first. In both cases, the output coding is straight

(natural) binary.

Sixteen serial clock cycles are required to perform a conversion

and to access data from the AD7441/AD7451. CS going low

provides the first leading zero to be read in by the DSP or the

microcontroller. The remaining data is then clocked out on the

subsequent SCLK falling edges, beginning with the second leading

zero. Thus, the first falling clock edge on the serial clock pro-

vides the second leading zero. The final bit in the data transfer

is valid on the 16th falling edge, having been clocked out on the

previous (15th) falling edge. Once the conversion is complete

and the data has been accessed after the 16 clock cycles, it is

important to ensure that, before the next conversion is initiated,

enough time is left to meet the acquisition and quiet-time speci-

fications (see the

and

sections). To achieve 1 MSPS with an 18 MHz clock, an 18-clock

burst performs the conversion and leaves enough time before the

next conversion for the acquisition and quiet time.

Timing Example 1

Timing Example 2

In applications with slower SCLKs, it is possible to read in data

on each SCLK rising edge; that is, the first rising edge of SCLK

after the CS falling edge has the leading zero provided, and the

15th SCLK edge has DB0 provided.