Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T

= 125°C (typ.).

Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1112: Micro SMD Wafer Level Chip Scale

Package (AN-1112).

Note 5: The human body model is a 100pF capacitor discharged through a 1.5k

Ω resistor into each pin. (MIL-STD-883 3015.7)

Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T

dissipation of the device in the application (P

following equation: T

Note 7: Junction-to-ambient thermal resistance is highly dependent on application and board layout. In applications where high maximum power dissipation

exists, special care must be paid to thermal dissipation issues in board design. For more information, please refer to National Semiconductor Application Note

1112: Micro SMD Wafer Level Chip Scale Package (AN-1112).

Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 9: C

Note 10: For the two groups of current sinks on a part (GroupA and GroupB), the following are determined: the maximum sink current in the group (MAX), the

minimum sink current in the group (MIN), and the average sink current of the group (AVG). For each group, two matching numbers are calculated: (MAX-AVG)/

AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure for the Group. The matching figure for a given part is

considered to be the highest matching figure of the two Groups. The typical specification provided is the most likely norm of the matching figure for all parts.

Note 11: For each Dxx pin, headroom voltage is the voltage across the internal current sink connected to that pin. For Group A, B, and C current sinks, V

V

Note 12: SCL and SDIO should be glitch-free in order for proper brightness control to be realized.

Note 13: SCL is tested with a 50% duty-cycle clock.

Block Diagram

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