12V)

-

CM

1

CMRR_dB

20

(

10

R

(2.048V

V

)

-

CMR

REF

´

(V ) +(V

) +(V

)

OS

OS_CM

OS_REF

2

2

2

V

V

OS_Total

SENSE

(Error_V ) +(Error_Gain) +(Error_Lin)

OS

2

2

2

INA282, INA283

INA284, INA285

INA286

www.ti.com

SBOS485A – NOVEMBER 2009 – REVISED JULY 2010

The nonlinearity error of the INA282-286 is relatively low compared to the gain error specification, which results

in a gain error that can be expected to be relatively constant throughout the linear input range of the device.

While the gain error remains constant across the linear input range of the device, the error associated with the

input offset voltage does not. As the differential input voltage developed across a shunt resistor at the input of the

INA282-286 decreases, the inherent input offset voltage of the device becomes a larger percentage of the

measured input signal resulting in an increase in error in the measurement. This varying error is present among

all current shunt monitors, given the input offset voltage ratio to the voltage being sensed by the device. The

relatively low input offset voltages present in the INA282-286 devices limit the amount of contribution the offset

voltage has on the total error term.

The term Reference Common-Mode Rejection refers to the amount of error induced by applying a reference

voltage to the INA282-286 device that deviates from the inherent bias voltage present at the output of the first

stage of the device. The output of the switched-capacitor network and first-stage amplifier has an inherent bias

voltage of approximately 2.048V. Applying a reference voltage of 2.048V to the INA282-286 reference pins

results in no additional error term contribution. Applying a voltage to the reference pins that differs from 2.048V

creates a voltage potential in the internal difference amplifier, resulting in additional current flowing through the

resistor network. As a result of resistor tolerances, this additional current flow causes additional error at the

output because of resistor mismatches. Additionally, as a result of resistor tolerances, this additional current flow

causes additional error at the output based on the common-mode rejection ratio of the output stage amplifier.

This error term is referred back to the input of the device as additional input offset voltage. Increasing the

difference between the 2.048V internal bias and the external reference voltage results in a higher input offset

voltage. Also, as the error at the output is referred back to the input, there is a larger impact on the input-referred

Two examples are provided that detail how different operating conditions can affect the total error calculations.

Typical and maximum calculations are shown as well to provide the user more information on how much error

variance could be present from device to device.

Example 1

Table 1. Example 1

TERM

SYMBOL

EQUATION

TYPICAL VALUE

MAXIMUM VALUE

Initial Input Offset

—

20mV

70mV

Voltage

Added Input Offset

Voltage Because of

0mV

0mV

Common-Mode

Voltage

Added Input Offset

Voltage Because of

0mV

0mV

Reference Voltage

Total Input Offset

20mV

70mV

Voltage

Error from Input

0.20%

0.70%

Offset Voltage

Gain Error

Error_Gain

—

0.40%

1.40%

Nonlinearity Error

Error_Lin

—

0.01%

0.01%

Total Error

—

0.45%

1.56%

Copyright © 2009–2010, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Link(s): INA282 INA283 INA284 INA285 INA286