ST6255C datasheet(9/84 Pages) STMICROELECTRONICS

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ST6255C ST6265C ST6265B

MEMORY MAP (Cont’d)

1.3.6

Data

RAM/EEPROM

Bank

(DRBR)

Address: E8h

—

Write only

Bit 7-5 = These bits are not used

Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2.

Bit 3-2 - Reserved. These bits are not used.

Bit 1 - DRBR1. This bit, when set, selects

EEPROM Page 1, when available.

Bit 0 - DRBR0. This bit, when set, selects

EEPROM Page 0, when available.

The selection of the bank is made by programming

the Data RAM Bank Switch register (DRBR regis-

ter) located at address E8h of the Data Space ac-

cording to Table 1. No more than one bank should

be set at a time.

The DRBR register can be addressed like a RAM

Data Space at the address E8h; nevertheless it is

a write only register that cannot be accessed with

single-bit operations. This register is used to select

the desired 64-byte RAM/EEPROM bank of the

Data Space. The bank number has to be loaded in

the DRBR register and the instruction has to point

to the selected location as if it was in bank 0 (from

00h address to 3Fh address).

This register is not cleared during the MCU initiali-

zation, therefore it must be written before the first

access to the Data Space bank region. Refer to

the Data Space description for additional informa-

tion. The DRBR register is not modified when an

interrupt or a subroutine occurs.

Notes:

Care is required when handling the DRBR register

as it is write only. For this reason, it is not allowed

to change the DRBR contents while executing in-

terrupt service routine, as the service routine can-

not save and then restore its previous content. If it

is impossible to avoid the writing of this register in

interrupt service routine, an image of this register

must be saved in a RAM location, and each time

the program writes to DRBR it must write also to

the image register. The image register must be

written first, so if an interrupt occurs between the

two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Other-

wise two or more pages are enabled in parallel,

producing errors.

Care must also be taken not to change the

E²PROM page (when available) when the parallel

writing mode is set for the E²PROM, as defined in

EECTL register.

Table 3. Data RAM Bank Register Set-up

DRBR

ST62T55C

ST62T65C/E65C

None

Not Available

EEPROM Page 0

Not Available

EEPROM Page 1

Not Available

10h

RAM Page 2

other

Reserved

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