www.irf.com

3

ART28XXT Series

1.

Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently

degrade performance and affect reliability.

2.

Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside

recommended limits is not specified.

3.

Parameter measured from 28V to 19 V or to 50V while loads remain fixed.

4.

Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.

5.

Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.

6.

Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.

7.

Load current is stepped for output under test while other outputs are fixed at half rated load.

8.

Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.

9.

A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the

maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.

10.

Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits

specified in the table.

11.

Load transient rate of change, di/dt

≤ 2 A/µSec.

12.

Recovery time is measured from the initiation of the transient to where V

13.

Line transient rate of change, dv/dt

≤ 50 V/µSec.

14.

Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the

input.

Notes to SPECIFICATIONS

Parameter

Symbol

Conditions

MIN

MAX

Units

Enable Input

open circuit voltage

drive current (sink)

voltage range

3.0

0.1

-0.5

5.0

50.0

V

mA

V

Synchronization Input

frequency range

pulse high level

pulse low level

pulse rise time

pulse duty cycle

External clock signal on Sync. input (pin 4)

225

4.5

-0.5

40

20

310

10.0

0.25

80

Khz

V

V

V/

µS

%

Synchronization Output

pulse high level

pulse low level

Signal compatible with synchronization input

3.7

0.0

4.3

0.25

V

Power dissipation, load fault

Short circuit, any output

16

W

Output response to step load

changes Notes 7, 11

10% Load to/from 50% load

50% Load to/from 100% load

-200

-200

200

200

Recovery time from step load

changes Notes 11, 12

10% Load to/from 50% load

50% Load to/from 100% load

200

200

µS

Output response to step line

changes Notes 10, 11

(main)

(dual)

-350

-1050

350

1050

Recovery time from step line

changes Notes 10, 11,13

(main)

(dual)

500

500

µS

Turn on overshoot

(main)

(dual)

100

500

mV

Turn on delay Note 14

5.0

20

mS

Capacitive load Notes 9, 10

CL

(main)

No effect on DC performance

(dual)

500

100

µF

Isolation

ISO

500VDC Input to Output or any pin to case

(except pin 12)

100

M

Ω

KHz

s

µs

µs

ms