ART10012TSLASHEM datasheet(4/12 Pages) IRF

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ART28XXT Series

Group A Tests V

IN= 28Volts, CL =0

unless otherwise specified.

Notes to Group A Test Table

Parameter verified during dynamic load regulation tests.

Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.

Load current is stepped for output under test while other outputs are fixed at half rated load.

Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.

Load step transition time

≥ 10µS.

Recovery time is measured from the initiation of the transient to where V

OUT has returned to within ±1% of its steady state value.

Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.

Subgroups 1 and 4 are performed at +25ºC, subgroups 2 and 5 at -55ºC and subgroups 3 and 6 at +125ºC.

Test

Symbol

Conditions unless otherwise specified

Group A

Subgroups

MIN

MAX

Units

Output voltage accuracy

VOUT

IOUT = 1.5 Adc

(main)

IOUT = ±250mAdc

ART2812(dual)

IOUT = ±250mAdc

ART2815(dual)

1, 2, 3

4.95

±11.70

±14.50

5.05

±12.30

±15.15

Output power Note 1

POUT

VIN = 19 V, 28V, 50 V

1, 2, 3

3.0

Output current

Note 1

IOUT

(main)

VIN 19 V, 28V, 50 V

(dual)

1, 2, 3

150

3000

500

Output regulation Note 4

IOUT = 150, 1500, 3000mAdc

(main)

VIN = 19 V, 28V, 50 V

IOUT = ±75, ±310, ±625mAdc

2812(dual)

IOUT = ±75, ±250, ±500mAdc

2815(dual)

1, 2, 3

4.8

±11.1

±14.0

5.2

±12.9

±15.8

Input current

IIN

IOUT = minimum rated, Pin 3 open

Pin 3 shorted to pin 2 (disabled)

1, 2, 3

250

8.0

Output ripple Note 2

VRIP

VIN = 19 V, 28V, 50 V

IOUT = 3000mA main, ±500mA dual

1, 2, 3

mVP-P

Input ripple Note 2

IRIP

VIN = 19 V, 28V, 50 V

IOUT = 3000mA main, ±500mA dual

1, 2, 3

100

mAP-P

Switching frequency

Synchronization pin (pin 6) open

4, 5, 6

225

275

KHz

Efficiency

Eff

IOUT = 3000mA main, ±500mA dual

2, 3

Power dissipation,

load fault

Short circuit, any output

1, 2, 3

Output response to step

load changes Notes 3, 5

VTL

10% Load to/from 50% load

50% Load to/from 100% load

4, 5, 6

-200

200

mVPK

Recovery time from step

load changes Notes 5, 6

TTL

10% Load to/from 50% load

50% Load to/from 100% load

4, 5, 6

200

µS

Turn on overshoot

VOS

(main)

IOUT = minimum and full rated

(dual)

4, 5, 6

100

500

Turn on delay Note 7

TDLY

IOUT = minimum and full rated

4, 5, 6

5.0

Isolation

ISO

500VDC Input to output or any pin to case

(except pin 12)

100

Ω

µs

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