CP80C86-2Z datasheet(21/37 Pages) INTERSIL

部件名	CP80C86-2Z

功能描述	CMOS 16-Bit Microprocessor

PDF	37 Pages

Scroll/Zoom	100%

制造商	INTERSIL [Intersil Corporation]

网页	http://www.intersil.com/cda/home

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21 / 37 page

FN2957.3

January 9, 2009

FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM

NOTE:

Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the

second INTA cycle.

Waveforms (Continued)

TDVCL

TCLDX1 (7)

TWHDX

TCVCTX

TCHCTV (30)

TCLAV

TCLAZ

TCHCTV

(31) TCVCTX

TCVCTV

(17)

(26)

(27)

(29) TCVCTV

DATA OUT

AD15-AD0

INVALID ADDRESS

CLK (82C84A OUTPUT)

WRITE CYCLE

(

RD, INTA,

DT/

R = VOH)

15-AD0

DEN

INTA CYCLE

(SEE NOTE)

(

RD, WR = VOH

BHE = VOL)

15-AD0

DT/

INTA

DEN

15-AD0

SOFTWARE

HALT -

DEN, RD,

WR, INTA = VOH

DT/

R = INDETERMINATE

SOFTWARE HALT

(29) TCVCTV

POINTER

TCL2CL1

(5)

TCLAV

TCLDV

TCLAX

(18)

TCLDX2

(29)

(28)

TWLWH

(38)

(29) TCVCTV

(19)

TCVCTX

(31)

(6)

(30)

(31)

(17)

TCH1CH2

(4)

80C86

CP80C86-2Z 数据表(PDF) 21 Page - Intersil Corporation

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