Chapter 1: Cyclone III Device Data Sheet

1–21

Switching Characteristics

© January 2010

Altera Corporation

Cyclone III Device Handbook, Volume 2

Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications (Note 1)

Symbol

Modes

C6

C7, I7

C8, A7

Unit

MinMax

MinMax

MinMax

f

clock frequency)

×10

10

420

10

370

10

320

MHz

×8

10

420

10

370

10

320

MHz

×7

10

420

10

370

10

320

MHz

×4

10

420

10

370

10

320

MHz

×2

10

420

10

370

10

320

MHz

×1

10

420

10

402.5

10

402.5

MHz

HSIODR

×10

100

840

100

740

100

640

Mbps

×8

80

840

80

740

80

640

Mbps

×7

70

840

70

740

70

640

Mbps

×4

40

840

40

740

40

640

Mbps

×2

20

840

20

740

20

640

Mbps

×1

10

420

10

402.5

10

402.5

Mbps

t

DUTY

—

455545

554555

%

TCCS

—

—

200—

200—

200ps

Output jitter

(peak to peak)

—

—

500—

500—

550ps

t

LOCK (2)

——

1

—

1

—

1

ms

Notes to Table 1–29:

(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).

Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (Note 1) (Part 1

of 2)

Symbol

Modes

C6

C7, I7

C8, A7

Unit

MinMax

MinMax

MinMax

f

frequency)

×10

10

320

10

320

10

275

MHz

×8

10

320

10

320

10

275

MHz

×7

10

320

10

320

10

275

MHz

×4

10

320

10

320

10

275

MHz

×2

10

320

10

320

10

275

MHz

×1

10

402.5

10

402.5

10

402.5

MHz

HSIODR

×10

100

640

100

640

100

550

Mbps

×8

80

640

80

640

80

550

Mbps

×7

70

640

70

640

70

550

Mbps

×4

40

640

40

640

40

550

Mbps

×2

20

640

20

640

20

550

Mbps

×1

10

402.5

10

402.5

10

402.5

Mbps

t

DUTY

—

45

55455545

55

%