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LM8322 数据表(PDF) 39 Page - National Semiconductor (TI) |
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LM8322 数据表(HTML) 39 Page - National Semiconductor (TI) |
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39 / 42 page ![]() 20.0 AC Electrical Characteristics (Temperature: -40°C ≤ T A ≤ +85°C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Parameter Conditions Min Typ Max Units System Clock (mclk) (Note 8) Internal RC 21 MHz 1.62V ≤ V CC ≤ 1.98V Processing and Command Execution Cycle (t C) (Note 8) 1.62V ≤ V CC ≤ 1.98V 0.5 μs System Clock, Processing and Command Execution Cycle Variation(Note 8) 7 % General-Purpose I/O (GPIO) Output Rise Time(Note 8) C LOAD = 50 pF 15 ns Output Fall Time(Note 8) 15 ns ACCESS.bus Input Signals(Note 9) Bus Free Time Between Stop and Start Condition (tBUFi) (Note 8) t SCLhigho SCL Setup Time (tCSTOsi) (Note 8) Before Stop Condition k 8 mclk SCL Hold Time (tCSTRhi) (Note 8) After Start Condition 8 mclk SCL Setup Time (tCSTRsi) (Note 8) Before Start Condition 8 mclk Data High Setup Time (tDHCsi) (Note 8) Before SCL Rising Edge (RE) 2 mclk Data Low Setup Time (tDLCsi) (Note 8) Before SCL RE 2 mclk SCL Low Time (tSCLlowi) (Note 8) After SCL Falling Edge (FE) 12 mclk SCL High Time (tSCLhighi) (Note 8) After SCL RE 12 mclk SDA Hold Time (tSDAhi) (Note 8) After SCL FE 0 mclk SDA Setup Time (tSDAsi) (Note 8) Before SCL RE 2 mclk ACCESS.bus Output Signals (Note 9) Bus Free Time Between Stop and Start Condition (tBUFo)(Note 9) t SCLhigho SCL Setup Time (tCSTOso) (Note 8) Before Stop Condition t SCLhigho SCL Hold Time (tCSTRho) (Note 8) After Start Condition t SCLhigho SCL Setup Time (tCSTRso) (Note 8) Before Start Condition t SCLhigho Data High Setup Time (tDHCso) (Note 8) Before SCL RE t SCLhigho Data Low Setup Time (tDLCso) (Note 8) Before SCL RE t SCLhigho SCL Low Time (tSCLlowo) (Note 8) After SCL FE 16 mclk SCL High Time (tSCLhigho) (Note 8) After SCL RE 16 mclk SDA Hold Time (tSDAho) (Note 8) After SCL FE 7 mclk SDA Valid Time (tSDAso) (Note 8) Before SCL RE 7 mclk Note 8: Guaranteed by design, not tested. Note 9: The ACCESS.bus interface implements and meets the timing necessary for interface to the I2C and SMBus protocol at logic levels. The bus drivers are designed with open-drain output for bidirectional operation. The will not meet the AC timing and current/voltage requirements of the full bus specification. 39 www.national.com |
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