LM5041ASD datasheet(3/16 Pages) NSC

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Pin Description (Continued)

NAME

DESCRIPTION

APPLICATION INFORMATION

PULL

Output of the push-pull drivers

Output of the push-pull gate driver. Output capability

of 1.5A peak.

PGND

Power ground

Connect directly to analog ground.

AGND

Analog ground

Connect directly to power ground.

Current sense input

Current sense input to the PWM comparator (CM

control). There is a 50ns leading edge blanking on

this pin. Using separate dedicated comparator, if CS

exceeds 0.5V the outputs will go into cycle by cycle

current limit.

Soft-start control

An external capacitor and an internal 10uA current

source, set the soft-start ramp.

TIME

Push-Pull overlap and dead time control

An external resistor (R

SET) sets the overlap time or

dead time for the push-pull outputs. A resistor

connected between TIME and GND produces

overlap. A resistor connected between TIME and

REF produces dead time.

RT / SYNC

Oscillator timing resistor pin and sync

An external resistor sets the oscillator frequency.

This pin will also accept an external oscillator.

UVLO

Line Under-Voltage Shutdown

An external divider from the power converter source

sets the shutdown levels. Threshold of operation

equals 2.5V. Hysteresis is set by a switched internal

current source (20µA).

LLP

DAP

SUB

Die substrate

The exposed die attach pad on the LLP package

should be connected to a PCB thermal pad at

ground potential. For additional information on using

National Semiconductor’s No Pull Back LLP

package, please refer to LLP Application Note

AN-1187.

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