DS3151_07 datasheet(21/61 Pages) MAXIM

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

21 of 61

SRIEn

Status Register Interrupt Enable

05h, 15h, 25h, 35h

Bit

Name

—

TDMIE

PRBSIE

PBERIE

RCVIE

RLOLIE

RLOSIE

Default

—

Bit 5: Transmitter Driver Monitor Interrupt Enable (TDMIE)

0 = mask TDML interrupt

1 = enable TDML interrupt

Bit 4: PRBS Detector Interrupt Enable (PRBSIE)

0 = mask PRBSL interrupt

1 = enable PRBSL interrupt

Bit 3: PRBS Detector Bit-Error Interrupt Enable (PBERIE)

0 = mask PBERL interrupt

1 = enable PBERL interrupt

Bit 2: Receiver Line-Code Violation Interrupt Enable (RCVIE)

0 = mask RCVL interrupt

1 = enable RCVL interrupt

Bit 1: Receiver Loss-of-Clock Lock Interrupt Enable (RLOLIE)

0 = mask RLOLL interrupt

1 = enable RLOLL interrupt

Bit 0: Receiver Loss-of-Signal Interrupt Enable (RLOSIE)

0 = mask RLOSL interrupt

1 = enable RLOSL interrupt

RCVLn

Receiver Code-Violation Count Register (Low Byte)

06h, 16h, 26h, 36h

Bit

Name

RCV[7]

RCV[6]

RCV[5]

RCV[4]

RCV[3]

RCV[2]

RCV[1]

RCV[0]

Default

RCVHn

Receiver Code-Violation Count Register (High Byte)

07h, 17h, 27h, 37h

Bit

Name

RCV[15]

RCV[14]

RCV[13]

RCV[12]

RCV[11]

RCV[10]

RCV[9]

RCV[8]

Default

Bits 15 to 0: Receiver Code-Violation Counter Register (RCV[15:0]). The RCV registers form a 16-bit register

for reading the line-code violation counter value. The registers are updated with the line-code violation counter

value when the RCVUD control bit is toggled low to high. After the RCV registers are updated, the line-code

violation counter is cleared. The counter operates in two modes, depending on the setting of the ITU bit in the RCR

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