DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

28 of 61

Figure 7-2. DS3 AIS Structure

M1 Subframe

X1

(1)

84

Info

Bits

F1

(1)

84

Info

Bits

C1

(0)

84

Info

Bits

F2

(0)

84

Info

Bits

C2

(0)

84

Info

Bits

F3

(0)

84

Info

Bits

C3

(0)

84

Info

Bits

F4

(1)

84

Info

Bits

M2 Subframe

X2

(1)

84

Info

Bits

F1

(1)

84

Info

Bits

C1

(0)

84

Info

Bits

F2

(0)

84

Info

Bits

C2

(0)

84

Info

Bits

F3

(0)

84

Info

Bits

C3

(0)

84

Info

Bits

F4

(1)

84

Info

Bits

M3 Subframe

P1

(0)

84

Info

Bits

F1

(1)

84

Info

Bits

C1

(0)

84

Info

Bits

F2

(0)

84

Info

Bits

C2

(0)

84

Info

Bits

F3

(0)

84

Info

Bits

C3

(0)

84

Info

Bits

F4

(1)

84

Info

Bits

M4 Subframe

P2

(0)

84

Info

Bits

F1

(1)

84

Info

Bits

C1

(0)

84

Info

Bits

F2

(0)

84

Info

Bits

C2

(0)

84

Info

Bits

F3

(0)

84

Info

Bits

C3

(0)

84

Info

Bits

F4

(1)

84

Info

Bits

M5 Subframe

M1

(0)

84

Info

Bits

F1

(1)

84

Info

Bits

C1

(0)

84

Info

Bits

F2

(0)

84

Info

Bits

C2

(0)

84

Info

Bits

F3

(0)

84

Info

Bits

C3

(0)

84

Info

Bits

F4

(1)

84

Info

Bits

M6 Subframe

M2

(1)

84

Info

Bits

F1

(1)

84

Info

Bits

C1

(0)

84

Info

Bits

F2

(0)

84

Info

Bits

C2

(0)

84

Info

Bits

F3

(0)

84

Info

Bits

C3

(0)

84

Info

Bits

F4

(1)

84

Info

Bits

M7 Subframe

M3

(0)

84

Info

Bits

F1

(1)

84

Info

Bits

C1

(0)

84

Info

Bits

F2

(0)

84

Info

Bits

C2

(0)

84

Info

Bits

F3

(0)

84

Info

Bits

C3

(0)

84

Info

Bits

F4

(1)

84

Info

Bits

Note 1: X1 is transmitted first.

Note 2: The 84 info bits contain the repetitive sequence 1010…, where the first 1 in the sequence immediately follows each X, P, F, C, or M bit.

8. DIAGNOSTICS

PRBS Generator and Detector. Each LIU has built-in pseudorandom bit sequence (PRBS) generator and detector

circuitry for physical layer testing. The device generates and detects unframed 2

PRBS, according to the ITU O.151 specification. To transmit a PRBS pattern, pull the TDSA and TDSB pins high

(hardware mode) or set configuration bits TDSA and TDSB (CPU bus mode). As Table 4-F shows, the PRBS

generator automatically generates 2

The PRBS detector, which is always enabled (Table 4-G), reports its status through the PRBS output pin (hardware

and CPU bus modes) or through the PRBS and PBER status bits (CPU bus mode). When the PRBS detector is out

of synchronization, the PRBS pin is forced high. When the detector syncs to an incoming PRBS pattern, the PRBS

pin is driven low, then pulses high, synchronous with RCLK, for each bit error detected. See Figure 8-1 and Figure

8-2 for details. In CPU bus mode, the PRBS status bit is set to one when the detector is out of synchronization and

set to zero when the detector syncs to an incoming PRBS pattern. A change of state of the PRBS bit can cause an

interrupt on the

INT pin if the PRBSIE interrupt-enable bit is set to one. A pattern bit error can also cause an

interrupt if the PBERIE interrupt-enable bit is set to one. The PRBS detector also declares sync in the presence of

an incoming all-ones pattern.