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ADS1178IPAPR 数据表(PDF) 21 Page - Texas Instruments

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部件名 ADS1178IPAPR
功能描述  Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters
PDF  39 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADS1178IPAPR 数据表(HTML) 21 Page - Texas Instruments

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DAISY-CHAINING
SYNC
CLK
SYNC
DIN
DOUT1
SCLK
SCLK
ADS1178
SYNC
DIN
CLK
CLK
DOUT1
DRDY
SerialDatafromDevices1and2
DRDY OutputfromDevice1
SCLK
ADS1178
U2
U1
DIN
CH1,U1
DOUT1
CH2,U1
CH3,U1
CH4,U1
CH5,U1
CH1,U2
CH2,U2
DIN2
SCLK
DRDY
(SPI)
FSYNC
(Frame-Sync)
1
2
17
33
18
34
49
50
65
66
129
130
145
146
257
258
ADS1174
ADS1178
www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008
The maximum number of channels that may be
daisy-chained in this way is limited by the frequency
Multiple ADS1174/78s can be daisy-chained together
of fSCLK, the mode selection, and the CLKDIV input.
to simplify the serial interface connections. The
The frequency of fSCLK must be high enough to
DOUT1 data output pin of one ADS1174/78 is
completely shift the data out from all channels within
connected to the DIN input of the next ADS1174/78.
one fDATA period. Table 12 lists the maximum number
As Figure 21 illustrates, the DOUT1 pin of device 1
of daisy-chained channels when fSCLK = fCLK.
provides the output data to a controller, and the DIN
input of device 2 is grounded. Figure 22 describes the
data format when reading data back in a daisy-chain
configuration.
Figure 21. Daisy-Chaining of Two ADS1178s, SPI Protocol (FORMAT[2:0] = 000 or 001)
Figure 22. Daisy-Chain Data Format of Figure 21
Table 12. Maximum Channels in a Daisy-Chain (fSCLK = fCLK)
MODE SELECTION
CLKDIV
MAXIMUM NUMBER OF CHANNELS
1
32
High-Speed
0
16
1
160
Low-Power
0
32
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): ADS1174 ADS1178



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