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SS22SDP2 数据表(PDF) 5 Page - Texas Instruments

部件名 SS22SDP2
功能描述  Contains all support circuitry needed for the ADS1174/ADS1274
PDF  48 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

SS22SDP2 数据表(HTML) 5 Page - Texas Instruments

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3.2
Data Output
www.ti.com
Digital Interface
Table 2. J5: Serial Interface Pins (continued)
Pin No.
Pin Name
Signal Name
I/O Type
Pullup
Function
J5.9
FSR
/DRDY/FSYNC
In/Out
None
J5.10
DGND
DGND
In/Out
None
Digital Ground
J5.11
DX
DIN
In
None
ADS1274 SPI data
in
J5.12
GPIO3
FORMAT1
In
High
J5.13
DR
DOUT1
Out
None
ADS1274 data out
J5.14
GPIO4
FORMAT2
In
None
J5.15
/INT
/DRDY/FSYNC
Out
None
J5.16
SCL
SCL
I2C
n/a
I2C clock
J5.17
TOUT
CLK
In
None
Can be used to
provide a clock from
a processor
J5.18
DGND
DGND
In/Out
None
Digital Ground
J5.19
GPIO5
CLK Select
None
J5.20
SDA
SDA
I2C
n/a
I2C data
Many pins on J5 have weak pull-up/pull-down resistors. These resistors provide default settings for many
of the control pins. Many pins on J5 correspond directly to ADS1274 pins. See the ADS1274 product data
sheet for complete details on these pins.
Most data communications are directed through DOUT1. The data from all eight channels can be
observed on the DOUT1 pin using the TDM mode. That is the signal used by the ADS1274EVM-PDK to
read back and display all the channels. All the data output signals (DOUT1 to DOUT4) can be monitored
on J2. Figure 2 illustrates the pinout for J2.
Figure 2. Connector J2
SBAU134A – August 2008 – Revised May 2009
ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK
5
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