M24256-DR datasheet(21/42 Pages) STMICROELECTRONICS

21 / 42 page

M24256-BF, M24256-BR, M24256-BW, M24256-DR

Device operation

Doc ID 6757 Rev 21

21/42

3.15

Current Address Read (in memory array)

For the Current Address Read operation, following a Start condition, the bus master only

sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges

this, and outputs the byte addressed by the internal address counter. The counter is then

incremented. The bus master terminates the transfer with a Stop condition, as shown in

Figure 11, without acknowledging the byte.

3.16

Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The

bus master does acknowledge the data byte output, and sends additional clock pulses so

that the device continues to output the next byte in sequence. To terminate the stream of

bytes, the bus master must not acknowledge the last byte, and must generate a Stop

condition, as shown in Figure 11.

The output data comes from consecutive addresses, with the internal address counter

automatically incremented after each byte output. After the last memory address, the

address counter ‘rolls-over’, and the device continues to output data from memory address

00h.

3.17

Read Identification Page

This instruction uses the same protocol and format as the Random Address Read (in

memory array) instruction. The only differences between the two instructions are that, in the

Read Identification Page instruction:

●

the device type identifier = 1011b

●

MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.

LSB address bits A5/A0 define the byte address inside the identification page. During a

Read Identification Page instruction, the (A5/A0) address should not exceed 3Fh.

M24256-DR 数据表(PDF) 21 Page - STMicroelectronics