M95128-RMB3GSLASHP datasheet(43/44 Pages) STMICROELECTRONICS

43 / 44 page

M95128, M95128-W, M95128-R

Revision history

Doc ID 5798 Rev 13

43/44

11-Jul-2008

M95128, device grade 3 devices is now offered at 10 MHz frequency.

Section 3.8: Supply voltage (VCC) on page 10 and Section 5.4: Write

Status Register (WRSR) on page 18 updated.

Table 15: DC characteristics (M95128-R) on page 29 modified.

tCH and tCL modified in Table 16: AC characteristics (M95128, device

grade 3) on page 30.

Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial

output timing modified.

Process A removed from Table 23: Ordering information scheme.

Small text changes.

17-Feb-2009

Section 3.8: Supply voltage (VCC) and Section 5.4: Write Status Register

(WRSR) updated.

Note added to Section 5.6: Write to Memory Array (WRITE).

ICC modified in Table 12: DC characteristics (M95128, device grade 3).

VRES added to DC characteristics tables 12, 13, 14 and 15.

Note added to Table 19: AC characteristics (M95128-R).

Note added below Figure 20: UFDFPN8, 8-lead ultra thin fine pitch dual

flat package no lead 2 x 3 mm, outline.

Small text changes.

12-Jan-2010

Section 5.6.1: ECC (error correction code) and write cycling modified

(applies to all devices).

TLEAD, IOL and IOH added to Table 6: Absolute maximum ratings.

Note added to Table 15: DC characteristics (M95128-R).

Process modified in Table 23: Ordering information scheme.

All packages are ECOPACK2 compliant.

02-Mar-2010

Section 5.6.1: ECC (error correction code) and write cycling and Table 24:

Available M95128x products (package, voltage range, temperature grade)

updated.

Table 25.

Document revision history (continued)

Date

Revision

Changes

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