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6402 数据表(PDF) 39 Page - Intel Corporation |
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6402 数据表(HTML) 39 Page - Intel Corporation |
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39 / 250 page ![]() Intel® 6400/6402 Advanced Memory Buffer Datasheet 39 Electrical, Power, and Thermal Idd_TDP_1 Total Power 5.8 6.4 W Idd_Active_1 Active Power L0 state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. @1.5 V 3.1 3.4 3.6 3.9 A @1.8 V 1.2 1.3 1.2 1.3 A @3.3 V A Idd_Active_1 Total Power 6.4 7.1 W Idd_Active_2 Active Power, data pass through L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled CKE high. Command and address lines stable. DRAM clock active. @1.5 V 2.9 3.2 3.3 3.7 A @1.8 V 0.6 0.7 0.6 0.7 A @3.3 V A Idd_Active_2 Total Power 5.0 5.6 W Idd_Training (for AMB spec, Not in SPD) Training Primary and Secondary channels enabled. 100% toggle on all channel lanes DRAMs idle. 0 BW. CKE high, Command and address lines stable. DRAM clock active. @1.5 V 3.5 4.0 A @1.8 V 0.7 0.7 A @3.3 V A Idd_Training Total Power W Idd_IBIST (for AMB spec, Not in SPD) IBIST Over all IBIST modes DRAM Idle (0 BW) Primary channel Enabled Secondary channel Enabled CKE high. Command and Address lines stable DRAM clock active @1.5 V 3.8 4.5 A @1.8 V 0.7 0.7 A @3.3 V A Idd_IBIST Total Power W Table 4-3. Power Values for x8 DIMMS (Sheet 2 of 3) 533 MHz 667 MHz Symbol Conditions Power Supply Thermal Design Max Current Thermal Design Max Current Units Notes |
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