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M93C46 数据表(PDF) 25 Page - STMicroelectronics |
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M93C46 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 37 page  M93C86, M93C76, M93C66, M93C56, M93C46 DC and AC parameters Doc ID 4997 Rev 10 25/37 Table 20. AC characteristics (M93Cx6, device grade 6 or 3) Test conditions specified in Table 12. and Table 9. Symbol Alt. Parameter Min. Max. Unit fC fSK Clock frequency D.C. 2 MHz tSLCH Chip Select low to Clock high 50 ns tSHCH tCSS Chip Select setup time M93C46, M93C56, M93C66 50 ns Chip Select setup time M93C76, M93C86 50 ns tSLSH (1) 1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles. tCS Chip Select low to Chip Select high 200 ns tCHCL (2) 2. tCHCL + tCLCH ≥ 1 / fC. tSKH Clock high time 200 ns tCLCH (2) tSKL Clock low time 200 ns tDVCH tDIS Data in setup time 50 ns tCHDX tDIH Data in hold time 50 ns tCLSH tSKS Clock setup time (relative to S) 50 ns tCLSL tCSH Chip Select hold time 0 ns tSHQV tSV Chip Select to READY/BUSY status 200 ns tSLQZ tDF Chip Select low to output Hi-Z 100 ns tCHQL tPD0 Delay to output low 200 ns tCHQV tPD1 Delay to output valid 200 ns tW tWP Erase or Write cycle time 5 ms Table 21. AC characteristics (M93Cx6-W, device grade 6) Test conditions specified in Table 13. and Table 10. Symbol Alt. Parameter Min. Max. Unit fC fSK Clock frequency D.C. 2 MHz tSLCH Chip Select low to Clock high 50 ns tSHCH tCSS Chip Select setup time 50 ns tSLSH (1) tCS Chip Select low to Chip Select high 200 ns tCHCL (2) tSKH Clock high time 200 ns tCLCH (2) tSKL Clock low time 200 ns tDVCH tDIS Data in setup time 50 ns tCHDX tDIH Data in hold time 50 ns tCLSH tSKS Clock setup time (relative to S) 50 ns tCLSL tCSH Chip Select hold time 0 ns tSHQV tSV Chip Select to READY/BUSY status 200 ns |
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