M41ST87WMX6F datasheet(17/52 Pages) STMICROELECTRONICS

17 / 52 page

M41ST87Y, M41ST87W

Operating modes

Doc ID 9497 Rev 8

17/52

2.3

WRITE mode

In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus

protocol is shown in Figure 12. Following the START condition and slave address, a logic '0'

(R/W = 0) is placed on the bus and indicates to the addressed device that word address An

will follow and is to be written to the on-chip address pointer. The data word to be written to

the memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The

M41ST87Y/W slave receiver will send an acknowledge clock to the master transmitter after

it has received the slave address (see Figure 9 on page 16) and again after it has received

the word address and each data byte.

Figure 12.

WRITE mode sequence

Figure 13.

WRITE cycle timing: RTC & external SRAM control signals

Available in SOX28 (MX) package only.

2.4

Data retention mode

With valid VCC applied, the M41ST87Y/W can be accessed as described above with READ

or WRITE cycles. Should the supply voltage decay, the M41ST87Y/W will automatically

deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD

(max) and VPFD (min) (see Figure 28 on page 46, Table 19 on page 46). This is

accomplished by internally inhibiting access to the clock registers. At this time, the reset pin

(RST) is driven active and will remain active until VCC returns to nominal levels. External

RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is

within 0.2 volts of the VBAT. ECON will remain at this level as long as VCC remains at an out-

of-tolerance condition. When VCC falls below the battery backup switchover voltage (VSO),

AI00591

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

AI03663

(1)

ECON

(1)

tEXPD

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