M41ST87W datasheet(15/52 Pages) STMICROELECTRONICS

15 / 52 page

M41ST87Y, M41ST87W

Operating modes

Doc ID 9497 Rev 8

15/52

Table 2.

AC characteristics

2.2

READ mode

In this mode the master reads the M41ST87Y/W slave after setting the slave address (see

Figure 9 on page 16). Following the WRITE mode control bit (R/W=0) and the acknowledge

bit, the word address 'An' is written to the on-chip address pointer. Next the START

condition and slave address are repeated followed by the READ mode control bit (R/W=1).

At this point the master transmitter becomes the master receiver.

The data byte which was addressed will be transmitted and the master receiver will send an

acknowledge bit to the slave transmitter. The address pointer is only incremented on

reception of an acknowledge clock. The M41ST87Y/W slave transmitter will now place the

data byte at address An+1 on the bus, the master receiver reads and acknowledges the new

byte and the address pointer is incremented to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter (see Figure 10 on page 16).

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume either due to a stop condition or when

the pointer increments to a non-clock or RAM address.

Note:

This is true both in READ mode and WRITE mode.

An alternate READ mode may also be implemented whereby the master reads the

M41ST87Y/W slave without first writing to the (volatile) address pointer. The first address

that is read is the last one stored in the pointer (see Figure 11 on page 16).

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).

Min

Max

Unit

fSCL

SCL clock frequency

400

kHz

tBUF

Time the bus must be free before a new transmission can start

1.3

µs

tEXPD

(2)

Available in SOX28 (MX) package only.

EX to ECON propagation delay

M41ST87Y

M41ST87W

SDA and SCL fall time

300

tHD:DAT

(3)

Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.

Data hold time

µs

tHD:STA

START condition hold time

(after this period the first clock pulse is generated)

600

tHIGH

Clock high period

600

tLOW

Clock low period

1.3

µs

SDA and SCL rise time

300

tSU:DAT

Data setup time

100

tSU:STA

START condition setup time

(only relevant for a repeated start condition)

600

tSU:STO

STOP condition setup time

600

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