STM809 datasheet(7/21 Pages) STMICROELECTRONICS

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STM809/810/811/812

Operation

Doc ID 9873 Rev 5

7/21

Operation

2.1

Reset output

The STM809/810/811/812 microprocessor reset circuit asserts a reset signal to the MCU

whenever VCC goes below the reset threshold (VRST), or when the push-button reset input

(MR) is taken low (see

Figure 14 on page 13). RST (active high for STM810/812) is

guaranteed valid down to VCC = 1 V (0° to 70°C).

During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for

the reset time-out period, trec. After this interval, RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

low for at least the reset time-out period. Any time VCC goes below the reset threshold, the

internal timer clears. The reset timer starts when VCC returns above the reset threshold. The

active-low reset (RST) and active-high reset (RST) both source and sink current.

2.2

Push-button reset input (STM811/812)

A logic low on MR asserts RST. RST remains asserted while MR is low, and for trec after it

returns high. The MR input has an internal 20 k

Ω pull-up resistor, allowing it to be left open if

not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector

outputs. Connect a normally open push-button switch from MR to GND to create a manual

reset function; external debounce circuitry is not required. If the device is used in a noisy

environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise

immunity.

2.3

Negative-going VCC transients

The STM809/810/811/812 are relatively immune to negative-going VCC transients (glitches).

Figure 12 on page 11 shows typical transient duration versus reset comparator overdrive

(for which the STM809/810/811/812 will NOT generate a reset pulse). The graph was

generated using a negative pulse applied to VCC, starting at 0.5V above the actual reset

threshold and ending below it by the magnitude indicated (comparator overdrive). The graph

indicates the maximum pulse width a negative VCC transient can have without causing a

reset pulse. As the magnitude of the transient increases (further below the threshold), the

maximum allowable pulse width decreases. Any combination of duration and overdrive

which lies under the curve will NOT generate a reset signal. Typically, a VCC transient that

goes 100 mV below the reset threshold and lasts 20 µs or less will not cause a reset pulse.

A 0.1 µF bypass capacitor mounted as close as possible to the VCC pin provides additional

transient immunity.

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