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CDK1307AILP40 数据表(PDF) 7 Page - Cadeka Microcircuits LLC.

部件名 CDK1307AILP40
功能描述  Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit Analog-to-Digital Converters (ADCs)
PDF  15 Pages
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制造商  CADEKA [Cadeka Microcircuits LLC.]
网页  http://www.cadeka.com
标志 CADEKA - Cadeka Microcircuits LLC.

CDK1307AILP40 数据表(HTML) 7 Page - Cadeka Microcircuits LLC.

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©2009 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Electrical Characteristics - CDK1307B
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
Signal to Noise Ratio
FIN = 2MHz
72.5
dBFS
FIN = 8MHz
71.9
72.7
dBFS
FIN ≃ FS/2
72
dBFS
FIN = 30MHz
70.8
dBFS
SINAD
Signal to Noise and Distortion Ratio
FIN = 2MHz
71.7
dBFS
FIN = 8MHz
71
72.1
dBFS
FIN ≃ FS/2
71.5
dBFS
FIN = 30MHz
71.2
dBFS
SFDR
Spurious Free Dynamic Range
FIN = 2MHz
81
dBc
FIN = 8MHz
75
81
dBc
FIN ≃ FS/2
80
dBc
FIN = 30MHz
80
dBc
HD2
Second order Harmonic Distortion
FIN = 2MHz
-90
dBc
FIN = 8MHz
-85
-95
dBc
FIN ≃ FS/2
-95
dBc
FIN = 30MHz
-90
dBc
HD3
Third order Harmonic Distortion
FIN = 2MHz
-81
dBc
FIN = 8MHz
-81
dBc
FIN ≃ FS/2
-75
-80
dBc
FIN = 30MHz
-80
dBc
ENOB
Effective number of Bits
FIN = 2MHz
11.6
bits
FIN = 8MHz
11.5
11.7
bits
FIN ≃ FS/2
11.6
bits
FIN = 30MHz
11.4
bits
Power Supply
AIDD
Analog Supply Current
13.4
mA
DIDD
Digital Supply Current
Digital core supply
1.7
mA
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT enabled
3.3
mA
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
2.4
mA
Analog Power Dissipation
24.1
mW
Digital Power Dissipation
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
9.1
mW
Total Power Dissipation
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
33.2
mW
Power Down Dissipation
9.7
μW
Sleep Mode
Power Dissipation, Sleep mode
14.2
mW
Clock Inputs
Max. Conversion Rate
40
MSPS
Min. Conversion Rate
20
MSPS



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