©2009 CADEKA Microcircuits LLC

www.cadeka.com

10

Data Sheet

Digital and Timing Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,

-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Clock Inputs

Duty Cycle

20

80

% high

Compliance

CMOS, LVDS, LVPECL, Sine Wave

Input Range

Differential input swing

pp

Differential input swing, sine wave clock input

pp

Input Common Mode Voltage

0.3

V

Differential

Timing

Start Up Time from Power Down

From Power Down Mode to Active Mode

900

clk cycles

SLP

Out Of Range Recovery Time

1

clk cycles

Aperture Delay

0.8

ns

Aperture Jitter

<0.5

ps

Pipeline Delay

12

clk cycles

Output Delay

ns

DC

ns

Logic Inputs

High Level Input Voltage

2

V

V

Low Level Input Voltage

0

0.8

V

0

V

High Level Input Leakage Current

-10

10

μA

Low Level Input Leakage Current

-10

10

μA

Input Capacitance

3

pF

Logic Outputs

High Level Output Voltage

V

Low Level Output Voltage

0.1

V

Max Capacitive Load

Post-driver supply voltage equal to pre-driver

supply voltage V

= V

5

pF

10

pF

Note:

(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents

and resulting switching noise at a minimum.

400

mV

1.6

V

Input Capacitance

2

pF

T

Start Up Time from Sleep

From Sleep Mode to Active Mode

clk cycles

20

10

3

5pF load on output bits (see timing diagram)

T

Output Delay Relative to CLK_EXT

See timing diagram

1

6

OVDD

VDVDD