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CDK1307DILP40 数据表(PDF) 3 Page - Cadeka Microcircuits LLC.

部件名 CDK1307DILP40
功能描述  Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit Analog-to-Digital Converters (ADCs)
PDF  15 Pages
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制造商  CADEKA [Cadeka Microcircuits LLC.]
网页  http://www.cadeka.com
标志 CADEKA - Cadeka Microcircuits LLC.

CDK1307DILP40 数据表(HTML) 3 Page - Cadeka Microcircuits LLC.

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©2009 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Pin No.
Pin Name
Description
23
D_4
Output Data
24
ORNG
Out of Range flag. High when input signal is out of range
27
CLK_EXT
Output clock signal for data synchronization. CMOS levels
28
D_5
Output Data
29
D_6
Output Data
30
D_7
Output Data
31
D_8
Output Data
32
D_9
Output Data
33
D_10
Output Data
34
D_11
Output Data (MSB for 1Vpp full scale range, see Reference Voltages section)
35
D_12
Output Data (MSB for 2Vpp full scale range)
38, 39
CM_EXTBC_1,
CM_EXTBC_0
Bias control bits for the buffer driving pin CM_EXT
00: OFF
01: 50μA
10: 500μA
11: 1mA
40
SLP_N
Sleep Mode when low
Pin Assignments
(Continued)



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