STM690 datasheet(16/42 Pages) STMICROELECTRONICS

16 / 42 page

Operation

STM690, STM704, STM795, STM802, STM804, STM805, STM806

16/42

Doc ID 10519 Rev 9

2.5

Chip enable gating (STM795 only)

Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the

external CMOS RAM in the event of an undervoltage condition. The STM795 uses a series

transmission gate from E to ECON (see Figure 11). During normal operation (reset not

asserted), the E transmission gate is enabled and passes all E transitions. When reset is

asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS

RAM. The short E propagation delay from E to ECON enables the STM795 to be used with

most µPs. If E is low when reset asserts, ECON remains low for typically 10 µs to permit the

current write cycle to complete.

2.6

Chip enable input (STM795 only)

The chip enable transmission gate is disabled and E is high impedance (disabled mode)

while reset is asserted. During a power-down sequence when VCC passes the reset

threshold, the chip enable transmission gate disables and E immediately becomes high

impedance if the voltage at E is high. If E is low when reset asserts, the chip enable

transmission gate will disable 10 µs after reset asserts (see Figure 12). This permits the

current write cycle to complete during power-down.

Any time a reset is generated, the chip enable transmission gate remains disabled and E

remains high impedance (regardless of E activity) for the first half of the reset time-out

period (trec/2). When the chip enable transmission gate is enabled, the impedance of E

appears as a 40

Ω resistor in series with the load at ECON. The propagation delay through

the chip enable transmission gate depends on VCC, the source impedance of the drive

connected to E, and the loading on ECON. The chip enable propagation delay is production

tested from the 50% point on E to the 50% point on ECON using a 50 Ω driver and a 50 pF

load capacitance (see Figure 35). For minimum propagation delay, minimize the capacitive

load at ECON and use a low-output impedance driver.

2.7

Chip enable output (STM795 only)

When the chip enable transmission gate is enabled, the impedance of ECON is equivalent to

a 40

Ω resistor in series with the source driving E. In the disabled mode, the transmission

gate is off and an active pull-up connects ECON to VOUT (see Figure 11). This pull-up turns

off when the transmission gate is enabled.

Figure 11.

Chip enable gating

AI08802

VRST

VOUT

VCC

COMPARE

ECON

trec

generator

ECON OUTPUT

CONTROL

RST

STM690 数据表(PDF) 16 Page - STMicroelectronics

STM690 数据表(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载