STM802 datasheet(14/42 Pages) STMICROELECTRONICS

14 / 42 page

Operation

STM690, STM704, STM795, STM802, STM804, STM805, STM806

14/42

Doc ID 10519 Rev 9

Operation

2.1

Reset output

The STM690/704/795/802/804/805/806 supervisor asserts a reset signal to the MCU

whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when

the push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic

high for STM804/805) for 0 V < VCC < VRST if VBAT is greater than 1 V. Without a backup

battery, RST is guaranteed valid down to VCC = 1 V.

During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for

the reset time-out period, trec. After this interval RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold

the internal timer clears. The reset timer starts when VCC returns above the reset threshold.

2.2

Push-button reset input (STM704/806)

A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see

Figure 36) after it returns high. The MR input has an internal 40 k

Ω pull-up resistor, allowing

it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with

open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND

to create a manual reset function; external debounce circuitry is not required. If MR is driven

from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor

from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when

not used.

2.3

Watchdog input (NOT available on STM704/795/806)

The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not

toggle the watchdog input (WDI) within tWD (1.6 s typ), the reset is asserted. The internal

watchdog timer is cleared by either:

a reset pulse, or

by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.

If WDI is tied high or low, a reset pulse is triggered every 1.8 s (tWD + trec).

The timer remains cleared and does not count for as long as reset is asserted. As soon as

reset is released, the timer starts counting (see Figure 37).

Note:

Input frequency greater than 20 ns (50 MHz) will be filtered.

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