STM802LM6F datasheet(36/43 Pages) STMICROELECTRONICS

36 / 43 page

DC and AC parameters

STM690A/692A/703/704/802/805/817/818/819

36/43

Doc ID 10522 Rev 10

tREC

RST pulse width

140

200

280

Push-button reset input (STM703/704/819)

tMLMH

tMR

MR pulse width

STM703/704

150

STM819

µs

tMLMR

tMRD MR to RST output delay

STM703/704

250

STM819

120

MR glitch immunity

STM819

100

MR pull-up resistor

MR = 0 V, VCC = 5 V

Watchdog timer (NOT available on STM703/704/819)

tWD

Watchdog timeout period

VRST (max) < VCC < 5.5 V

1.12

1.60

2.24

WDI pulse width

VRST (max) < VCC < 5.5 V

Chip-enable gating (STM818 only)

E to ECON resistance

VCC = VRST (max)

150

E to ECON propagation

delay

4.5 V < VCC < 5.5 V

Reset to ECON high delay

(Power-down)

µs

ECON short circuit current

VCC = 5 V, disable mode,

E = logic high, ECON = 0 V

0.1

0.75

2.0

Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.75 V to 5.5 V for “L” versions; VCC = 4.5 V to 5.5 V for

“M” versions; and VBAT = 2.8 V (except where noted).

VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality, state of

RST

and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC (min).

Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V.

VCC (min) = 1.0 V for TA = 0 °C to +85 °C.

Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.

Guaranteed by design.

WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output

device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device

must also be able to source and sink at least 200 µA when active.

When VBAT > VCC > VRST, VOUT remains connected to VCC until VCC drops below VRST.

When VRST > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV.

For VCC falling.

Table 7.

DC and AC characteristics (continued)

Sym

Alter-

native

Description

Test condition(1)

Min

Typ

Max

Unit

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