STM6717/6718/6719/6720/STM6777/6778/6779/6780

DC and AC parameters

Doc ID 11469 Rev 7

21/30

Manual (push-button) reset input

MR input voltage

C1

V

V

MR minimum pulse width

(STM6717/18/19/20)

1µs

MR minimum pulse width

(STM6777/78/79/80)

MRC connected via

(5)

6µs

MR to RST output delay

200

ns

MR glitch immunity

(STM6717/18/19/20)

100

ns

MR pull-up resistance

25

50

80

k

Ω

1.

noted).

2.

Input leakage for the MRC pin is not tested.

3.

Guaranteed by design.

4.

The leakage current measured on the RST pin is tested with the reset de-asserted (output high impedance).

5.

Selecting the appropriate external capacitor (preferably less than 100 pF) allows systems designers to vary the minimum

delay from 6µs (MRC pin left open) or more (see Table 7).

Table 6.

DC and AC characteristics (continued)

Sym

Alter-

native

Description

Min

Typ

Max

Unit

Table 7.

100 pF

0.1 µF

2.2 µF

3.3 µF

4.7 µF

6.8 µF

1.6 V

120 µs

120 ms

2.6 s

4.0 s

5.6 s

8.2 s

2.0 V

122 µs

122 ms

2.7 s

4.0 s

5.8 s

8.3 s

3.0 V

125 µs

125 ms

2.7 s

4.1 s

5.9 s

8.5 s

4.0 V

128 µs

129 ms

2.8 s

4.2 s

6.0 s

8.7 s

5.0 V

130 µs

130 ms

2.8 s

4.3 s

6.1 s

8.8 s

1.

At 25 °C (typical)