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ST10F272Z2 数据表(PDF) 105 Page - STMicroelectronics

部件名 ST10F272Z2
功能描述  16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
PDF  189 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F272Z2 数据表(HTML) 105 Page - STMicroelectronics

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ST10F272Z2
System reset
105/189
The start-up configurations and some system features are selected on reset sequences as
described in Table 51 and Figure 35.
Table 51 describes what is the system configuration latched on PORT0 in the six different
reset modes. Figure 35 summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.
Software Reset (2)
x
0
N
Synch.
Not activated
0
0
0
1
0
x
0
N
Synch.
Not activated
0
0
0
1
0
0
1
Y
Synch.
Not activated
0
0
0
1
0
1
1
Y
Synch.
Activated by internal logic for 1024 TCL
0
0
0
1
0
Watchdog Reset (2)
x
0
N
Synch.
Not activated
0
0
0
1
1
x
0
N
Synch.
Not activated
0
0
0
1
1
0
1
Y
Synch.
Not activated
0
0
0
1
1
1
1
Y
Synch.
Activated by internal logic for 1024 TCL
0
0
0
1
1
1.
It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details).
2.
When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently
flagged (see Section 20.6 for details).
Table 50.
Reset event (continued)
Event
RSTIN
WDTCON Flags
min
max
Table 51.
PORT0 latched configuration for the different reset events
X: Pin is sampled
-: Pin is not sampled
PORT0
Sample event
Software Reset
-
-
-
XX
XX
XX
X
-
-
-
-
-
-
Watchdog Reset
-
-
-
XX
XX
XX
X
-
-
-
-
-
-
Synchronous Short Hardware Reset
-
-
-
XX
XX
XX
XXX
XX
XX
Synchronous Long Hardware Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Asynchronous Hardware Reset
X
X
XXX
XX
XX
XXX
XX
XX
Asynchronous Power-On Reset
X
X
XXX
XX
XX
XXX
XX
XX



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