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ST10F272Z2 数据表(PDF) 128 Page - STMicroelectronics |
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ST10F272Z2 数据表(HTML) 128 Page - STMicroelectronics |
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128 / 189 page ![]() Known limitations ST10F272Z2 128/189 24 Known limitations This section describes all functional and electrical limitations identified on the silicon revision A of the ST10F272Z2. They are listed in Table 60: List of limitations on page 128 The revision number of the device can be read in the IDCHIP register (@F07Ch) which is set to 1102h for this device (refer to 23.4: Identification registers). Table 60. List of limitations Limitation 24.1: Injected conversion stalling the ADC 24.2: Concurrent transmission requests in DAR-mode (C-CAN module) 24.3: Transmission request disabled (C-CAN module) 24.4: Spurious BREQ pulse in slave mode during external bus arbitration phase 24.5: Flash wake-up from idle mode 24.6: Executing PWRDN instruction 24.7: Flash wake-up from Power Down mode 24.8: Behavior of CAPCOM outputs in COMPARE mode 3 |
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