ST10F272Z2_08 datasheet(155/189 Pages) STMICROELECTRONICS

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ST10F272Z2

Electrical characteristics

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25.8

AC characteristics

25.8.1

Test waveforms

Figure 46.

Input / output waveforms

Figure 47.

Float waveforms

25.8.2

Definition of internal timing

The internal operation of the ST10F272Z2 is controlled by the internal CPU clock fCPU. Both

edges of the CPU clock can trigger internal (for example pipeline) or external (for example

bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time

between two consecutive edges of the CPU clock, called “TCL”.

The CPU clock signal can be generated by different mechanisms. The duration of TCL and

its variation (and also the derived external timing) depends on the mechanism used to

generate fCPU.

This influence must be regarded when calculating the timings for the ST10F272Z2.

The example for PLL operation shown in Figure 48 refers to a PLL factor of 4.

The mechanism used to generate the CPU clock is selected during reset by the logic levels

on pins P0.15-13 (P0H.7-5).

2.4V

0.4V

Test Points

2.0V

0.8V

AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.

Timing measurements are made at VIH min. for a logic ‘1’ and VIL max for a logic ‘0’.

Timing

Reference

Points

VLOAD + 0.1V

VLOAD - 0.1V

VOH - 0.1V

VOL + 0.1V

VLOAD

VOL

VOH

For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.

It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20m

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