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ST10F272Z2 数据表(PDF) 166 Page - STMicroelectronics |
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ST10F272Z2 数据表(HTML) 166 Page - STMicroelectronics |
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166 / 189 page  Electrical characteristics ST10F272Z2 166/189 25.8.16 Multiplexed bus VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125 °C, CL = 50 pF, ALE cycle time = 6 TCL + 2tA + tC + tF (75 ns at 40 MHz CPU clock without wait states) Table 79. Multiplexed bus timings Symbol Parameter FCPU = 40 MHz TCL = 12.5 ns Variable CPU Clock 1/2 TCL = 1 to 64 MHz min. max. min. max. t5 CC ALE high time 4 + tA – TCL – 8.5 + tA –ns t6 CC Address setup to ALE 1.5 + tA – TCL – 11 + tA –ns t7 CC Address hold after ALE 4 + tA – TCL – 8.5 + tA –ns t8 CC ALE falling edge to RD, WR (with RW-delay) 4 + tA – TCL – 8.5 + tA –ns t9 CC ALE falling edge to RD, WR (no RW-delay) – 8.5 + tA – – 8.5 + tA –ns t10 CC Address float after RD, WR (with RW-delay)1 –6 – 6 ns t11 CC Address float after RD, WR (no RW-delay)1 – 18.5 – TCL + 6 ns t12 CC RD, WR low time (with RW-delay) 15.5 + tC – 2TCL – 9.5 + tC –ns t13 CC RD, WR low time (no RW-delay) 28 + tC – 3TCL – 9.5 + tC –ns t14 SR RD to valid data in (with RW-delay) –6 + tC – 2TCL – 19 + tC ns t15 SR RD to valid data in (no RW-delay) –18.5 + tC – 3TCL – 19 + tC ns t16 SR ALE low to valid data in – 17.5 + + tA + tC – 3TCL – 20 + + tA + tC ns t17 SR Address/Unlatched CS to valid data in – 20 + 2tA + + tC – 4TCL – 30 + + 2tA + tC ns t18 SR Data hold after RD rising edge 0– 0 – ns t19 SR Data float after RD1 – 16.5 + tF – 2TCL – 8.5 + tF ns t22 CC Data valid to WR 10 + tC – 2TCL – 15 + tC –ns t23 CC Data hold after WR 4 + tF – 2TCL – 8.5 + tF –ns t25 CC ALE rising edge after RD, WR 15 + tF – 2TCL – 10 + tF –ns t27 CC Address/Unlatched CS hold after RD, WR 10 + tF – 2TCL – 15 + tF –ns t38 CC ALE falling edge to Latched CS – 4 – tA 10 – tA – 4 – tA 10 – tA ns |
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