ST10F272Z2_08 datasheet(173/189 Pages) STMICROELECTRONICS

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ST10F272Z2

Electrical characteristics

173/189

RW-delay and tA refer to the next following bus cycle.

Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

Partially tested, guaranteed by design characterization.

t38

ALE falling edge to Latched

– 4 – tA

6 – tA

– 4 – tA

6 – tA

t39

Latched CS low to Valid Data

–

16.5 +

+ tC + 2tA

–

3TCL – 21 +

+ tC + 2tA

t41

Latched CS hold after RD,

2 + tF

–

TCL – 10.5 + tF

–ns

t82

Address setup to RdCS,

WrCS

(with RW-delay)

14 + 2tA

–

2TCL – 11 + 2tA

–ns

t83

Address setup to RdCS,

WrCS

(no RW-delay)

2 + 2tA

–

TCL –10.5 + 2tA

–ns

t46

RdCS to Valid Data In

(with RW-delay)

–4 + tC

–

2TCL – 21 + tC

t47

RdCS to Valid Data In

(no RW-delay)

–16.5 + tC

–

3TCL – 21 + tC

t48

RdCS, WrCS Low Time

(with RW-delay)

15.5 + tC

–

2TCL – 9.5 + tC

–ns

t49

RdCS, WrCS Low Time

(no RW-delay)

28 + tC

–

3TCL – 9.5 + tC

–ns

t50

Data valid to WrCS

10 + tC

–

2TCL – 15 + tC

–ns

t51

Data hold after RdCS

0–

–

t53

Data float after RdCS

(with RW-delay) 3

–

16.5 + tF

–

2TCL – 8.5 + tF

t68

Data float after RdCS

(no RW-delay) 3

–4 + tF

–

TCL – 8.5 + tF

t55

Address hold after

RdCS, WrCS

– 8.5 + tF

–

– 8.5 + tF

–ns

t57

Data hold after WrCS

2 + tF

–

TCL – 10.5 + tF

–ns

Table 80.

Demultiplexed bus timings (continued)

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU Clock

1/2 TCL = 1 to 64 MHz

min.

max.

min.

max.

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