M95256-D-CS3GSLASHK datasheet(18/48 Pages) STMICROELECTRONICS

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Instructions

M95256-DR, M95256, M95256-W, M95256-R

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Doc ID 12276 Rev 11

5.4

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

previously executed.

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code, the data byte on Serial Data Input (D) and the Chip Select

(S) driven High. Chip Select (S) must be driven High after the rising edge of Serial Clock (C)

that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock

(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed.

The instruction sequence is shown in Figure 9.

Driving the Select (S) High at a byte boundary of the input data triggers the self timed Write

cycle, and continues for a period tW (as specified in Table 17, Table 18, Table 19 and

Table 20). While the Write Status Register cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-

timed Write cycle tW, and is 0 when the Write cycle is completed. The WEL bit (Write Enable

Latch) is also reset when the Write cycle tW is completed.

The Write Status Register (WRSR) instruction allows the user to change the values of the

BP1, BP0 bits and the SRWD bit:

●

The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as

read only, as defined in Table 2.

●

The SRWD bit (Status Register Write Disable bit), in accordance with the signal read

on the Write Protect pin (W), allows the user to set or reset the Write protection mode

of the Status Register itself, as defined in Table 6 When in Write Protected mode, the

Write Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the

WRSR instruction, including the tW Write cycle.

The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1, b0 of the

Status Register. Bits b6, b5, b4 are always read as 0.

Table 6.

Protection modes

W signal

SRWD

bit

Mode

Write protection of the

Status Register

Memory content

Protected area(1)

As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6.

Unprotected area(1)

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the BP1

and BP0 bits can be

changed

Write-protected

Ready to accept Write

instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write

protected

The values in the BP1

and BP0 bits cannot be

changed

Write-protected

Ready to accept Write

instructions

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