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XC161CS-32F 数据表(PDF) 72 Page - Infineon Technologies AG |
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XC161CS-32F 数据表(HTML) 72 Page - Infineon Technologies AG |
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72 / 87 page ![]() XC161CS-32F Derivatives Electrical Parameters Data Sheet 70 V1.2, 2006-08 4.4.3 External Clock Drive XTAL1 Figure 16 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the oscillator frequency is limited to a range of 4 MHz to 16 MHz. It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is verified by design only (not subject to production test). Table 19 External Clock Drive Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Min. Max. Oscillator period t OSC SR 25 2501) 1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL. ns High time2) 2) The clock input signal must reach the defined levels VILC and VIHC. t 1 SR 6–ns Low time2) t 2 SR 6–ns Rise time2) t 3 SR –8ns Fall time2) t 4 SR –8ns MCT05572 t 1 t 2 t OSC t 3 t 4 0.5 V DDI V ILC V IHC |
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