PD-60325

iP2005APbF

Figure 13 Top & Bottom Component and Via Placement (Topside, Transparent view down)

PCB Layout Guidelines

The following guidelines are recommended to reduce the parasitic values and optimize

overall performance.

• All pads on the iP2005A footprint design need to be Solder-mask defined (see Figure 12).

Also refer to International Rectifier application notes AN1028 and AN1029 for further

footprint design guidance.

• Place as many vias around the Power pads (V

optimal thermal performance.

• A minimum of six 10µF, X5R, 16V ceramic capacitors per iP2005A are needed for greater

than 30A operation. This will result in the lowest loss due to input capacitor ESR.

• Placement of the ceramic input capacitors is critical to optimize switching performance. In

cases where there is a heatsink on the case of iP2005A, place all six ceramic capacitors

right underneath the iP2005A footprint (see Figure 13 Bottom Component Layer). In

cases where there is not heatsink, C1 and C6 on the bottom layer may be moved to the

C1x and C6x locations (respectively) on the top component layer (see Figure 13 Top

Component Layer). In both cases, C2 – C5 need to be placed right underneath the

iP2005A PCB footprint.

• Dedicate at least two layer to for P

• Duplicate the Power Nodes on multiple layers (refer to AN1029).

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