PROGRAMMING THE OUTPUT VOLTAGE (LP4951C)

The LP4951C may be pin-strapped for 5V using its internal

voltage divider by tying the pin 1 (output) to pin 2 (sense)

pins together, and also tying the pin 7 (feedback) and pin 6

(V

any output voltage between its 1.235V reference and its 30V

maximum rating. As seen in Figure 2, an external pair of

resistors is required.

The complete equation for the output voltage is

where V

the feedback pin bias current, nominally −20 nA. The mini-

mum recommended load current of 1µA forces an upper limit

of 1.2 M

Ω on the value of R

no load (a condition often found in CMOS in standby). I

produce a 2% typical error in V

at room temperature by trimming R

choosing R

creasing the resistor program current to 12µA. Since the

LP4951C typically draws 60µA at no load with Pin 2 open-

circuited, this is a small price to pay.

REDUCING OUTPUT NOISE

In reference applications it may be advantageous to reduce

the AC noise present at the output. One method is to reduce

the regulator bandwidth by increasing the size of the output

capacitor. This is the only way noise can be reduced on the

3 lead LP4950C but is relatively inefficient, as increasing the

capacitor from 1µF to 220µF only decreases the noise from

430µV to 160µV rms for a 100kHz bandwidth at 5V output.

Noise can be reduced fourfold by a bypass capacitor across

R

Pick

or about 0.01µF. When doing this, the output capacitor must

be increased to 3.3µF to maintain stability. These changes

reduce the output noise from 430µV to 100µV rms for a

100kHz bandwidth at 5V output. With the bypass capacitor

added, noise no longer scales with output voltage so that

improvements are more dramatic at higher output voltages.

20052820

voltage (see Figure 2), rather than an external 5V source, will keep the

error flag voltage under 1.2V (typ.) in this condition. The user may wish to

divide down the error flag voltage using equal-value resistors (10 k

Ω

suggested), to ensure a low-level logic signal during any fault condition,

while still allowing a valid high logic level during normal operation.

FIGURE 1. ERROR Output Timing

20052807

*See Application Hints

**Drive with TTL-high to shut down. Ground or leave open if shutdown

feature is not to be used.

Note: Pins 2 and 6 are left open.

FIGURE 2. Adjustable Regulator (LP4951C)

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