MF1ICS50_001056

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Product data sheet

PUBLIC

Rev. 5.6 — 24 November 2010

001056

4 of 20

NXP Semiconductors

MF1ICS50

Functional specification

6.

Functional description

6.1 Block description

The MF1ICS50 chip consists of the 1 Kbyte EEPROM, the RF-Interface and the Digital

Control Unit. Energy and data are transferred via an antenna, which consists of a coil with

a few turns directly connected to the MF1ICS50. No further external components are

necessary. (For details on antenna design please refer to the document MIFARE‚ Card IC

Coil Design Guide.)

– Modulator/Demodulator

– Rectifier

– Clock Regenerator

– Power On Reset

– Voltage Regulator

ensures that access to a block is only possible via the two keys specified for each

block

can be incremented and decremented

and encryption of data exchange.

16 bytes. The last block of each sector is called “trailer”, which contains two secret

keys and programmable access conditions for each block in this sector.

6.2 Communication principle

The commands are initiated by the reader and controlled by the Digital Control Unit of the

MF1ICS50 according to the access conditions valid for the corresponding sector.

6.2.1 Request standard/ all

After Power On Reset (POR) of a card it can answer to a request command - sent by the

reader to all cards in the antenna field - by sending the answer to request code (ATQA

according to ISO/IEC 14443A).

6.2.2 Anticollision loop

In the anticollision loop the serial number of a card is read. If there are several cards in the

operating range of the reader, they can be distinguished by their unique serial numbers

and one can be selected (select card) for further transactions. The unselected cards

return to the standby mode and wait for a new request command.