MPC8343CZQADDB datasheet(4/79 Pages) FREESCALE

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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Overview

— Address translation units for address mapping between host and peripheral

— Dual address cycle for target

— Internal configuration registers accessible from PCI

•

Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four

crypto-channels, a controller, and a set of crypto execution units (EUs):

— Public key execution unit (PKEU) :

– RSA and Diffie-Hellman algorithms

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard (DES) execution unit (DEU)

– DES and 3DES algorithms

– Two key (K1, K2) or three key (K1, K2, K3) for 3DES

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric-key cipher

– Key lengths of 128, 192, and 256 bits

– ECB, CBC, CCM, and counter (CTR) modes

— XOR parity generation accelerator for RAID applications

— ARC four execution unit (AFEU)

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Stream cipher compatible with the RC4 algorithm

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40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160-, 224-, or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units through an integrated controller

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Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

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Universal serial bus (USB) dual role controller

— USB on-the-go mode with both device and host functionality

— Complies with USB specification Rev. 2.0

— Can operate as a stand-alone USB device

– One upstream facing port

– Six programmable USB endpoints

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