MPC8343EVRAGDB datasheet(2/79 Pages) FREESCALE

2 / 79 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Overview

NOTE

The information in this document is accurate for revision 3.x silicon and

later (in other words, for orderable part numbers ending in A or B). For

information on revision 1.1 silicon and earlier versions, see the MPC8343E

PowerQUICC II Pro Integrated Host Processor Hardware Specifications.

See Section 22.1, “Part Numbers Fully Addressed by This Document,” for

silicon revision level determination.

Overview

This section provides a high-level overview of the device features. Figure 1 shows the major functional

units within the MPC8343EA.

Figure 1. MPC8343EA Block Diagram

Major features of the device are as follows:

•

Embedded PowerPC e300 processor core; operates at up to 400 MHz

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

— 32-Kbyte instruction cache, 32-Kbyte data cache

— Lockable portion of L1 cache

— Dynamic power management

— Software-compatible with the other Freescale processor families that implement Power

Architecture technology

•

Double data rate, DDR1/DDR2 SDRAM memory controller

— Programmable timing supporting DDR1 and DDR2 SDRAM

— 32- bit data interface, up to 266 MHz data rate

DUART

Dual I2C

Timers

GPIO

Security

Interrupt

Controller

Dual

Role

High-Speed

Local Bus

DDR

SDRAM

Controller

32KB

D-Cache

e300 Core

32KB

I-Cache

USB 2.0

10/100/1000

SEQ

PCI

DMA

Ethernet

10/100/1000

Ethernet

MPC8343EVRAGDB 数据表(PDF) 2 Page - Freescale Semiconductor, Inc

MPC8343EVRAGDB 数据表(HTML) 2 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

数据表下载