MPC8572ECLPXAULD datasheet(6/140 Pages) FREESCALE

6 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– NAND Flash control machine (FCM)

— Parity support

— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)

•

Four enhanced three-speed Ethernet controllers (eTSECs)

— Three-speed support (10/100/1000 Mbps)

— Four IEEE Std 802.3™, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab-compatible controllers

— Support for various Ethernet physical interfaces:

– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, RGMII and SGMII

– 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII

— Flexible configuration for multiple PHY interface configurations

— TCP/IP acceleration and QoS features available

– IP v4 and IP v6 header recognition on receive

– IP v4 header checksum verification and generation

– TCP and UDP checksum verification and generation

– Per-packet configurable acceleration

– Recognition of VLAN, stacked (Q-in-Q) VLAN, 802.2, PPPoE session, MPLS stacks, and

ESP/AH IP-security headers

– Supported in all FIFO modes

— Quality of service support:

– Transmission from up to eight physical queues

– Reception to up to eight physical queues

— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):

– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or

software-programmed PAUSE frame generation and recognition)

— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and

IEEE Std 802.1™ virtual local area network (VLAN) tags and priority

— VLAN insertion and deletion

– Per-frame VLAN control word or default VLAN for each eTSEC

– Extracted VLAN control word passed to software separately

— Retransmission following a collision

— CRC generation and verification of inbound/outbound frames

— Programmable Ethernet preamble insertion and extraction of up to 7 bytes

— MAC address recognition:

– Exact match on primary and virtual 48-bit unicast addresses

– VRRP and HSRP support for seamless router fail-over

MPC8572ECLPXAULD 数据表(PDF) 6 Page - Freescale Semiconductor, Inc

MPC8572ECLPXAULD 数据表(HTML) 6 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载