MPC8572ECPXATLD datasheet(2/140 Pages) FREESCALE

2 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.

— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

— 36-bit real addressing

— Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

— Enhanced hardware and software debug support

— Performance monitor facility that is similar to, but separate from, the MPC8572E performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some

features that this device implements more specifically. An understanding of these differences can

be critical to ensure proper operation.

•

1 Mbyte L2 cache/SRAM

— Shared by both cores.

— Flexible configuration and individually configurable per core.

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

– 1, 2, or 4 ways can be configured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and Flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be Flash cleared separately.

— Per-way allocation of cache region to a given processor.

— SRAM features include the following:

– 1, 2, 4, or 8 ways can be configured as SRAM.

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for

smaller-than-cache-line accesses.

•

e500 coherency module (ECM) manages core and intra-system transactions

•

Address translation and mapping unit (ATMU)

— Twelve local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI Express

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